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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Arumi Delgado, Daniel |
dc.contributor.author | Figueras Pàmies, Joan |
dc.contributor.author | Eichenberger, S. |
dc.contributor.author | Hora, Camelia |
dc.contributor.author | Kruseman, B. |
dc.date | 2007-10 |
dc.identifier.citation | Rodriguez, R. [et al.]. Impact of gate tunnelling leakage on CMOS circuits with full open defects. "Electronics Letters", Octubre 2007, vol. 43, núm. Issue 21, p. 1140-1141. |
dc.identifier.citation | 0013-5194 |
dc.identifier.citation | 10.1049/el:20072117 |
dc.identifier.uri | http://hdl.handle.net/2117/20118 |
dc.language.iso | eng |
dc.publisher | Institution of Electrical Engineers |
dc.relation | http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=4349252&isnumber=4349241&punumber=2220&k2dockey=4349252@ieejrns&query=%28%28arume%29%3Cin%3Emetadata+%29&pos=0 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Metal oxide semiconductors, Complementary |
dc.subject | CMOS integrated circuits |
dc.subject | Circuits integrats -- CMOS -- Disseny i construcció |
dc.title | Impact of gate tunnelling leakage on CMOS circuits with full open defects |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
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