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Transactional access to shared memory in StarSs, a task based programming model
Gayatri, Rahulkumar; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Lujan, M; Watson, I.
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
With an increase in the number of processors on a single chip, programming environments which facilitate the exploitation of par- allelism on multicore architectures have become a necessity. StarSs is a task-based programming model that enables a flexible and high level programming. Although task synchronization in StarSs is based on data flow and dependency analysis, some applications (e.g. reductions )require locks to access shared data. Transactional Memory is an alternative to lock-based synchronization for controlling access to shared data. In this paper we explore the idea of integrating a lightweight Software Transactional Memory (STM) library, TinySTM , into an implementation of StarSs (SMPSs). The SMPSs run- time and the compiler have been modified to include and use calls to the STM library. We evaluated this approach on four applications and observe better performance in applications with high lock contention.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Computer architecture
Data flow
Dependency analysis
High-level programming
Lock-based synchronization
Multicore architectures
Programming environment
Programming models
Runtimes
Shared data
Shared memories
Single chips
Software transactional memory
STM Library
Task synchronization
Task-based
Transactional memory
Arquitectura d'ordinadors
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