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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Pérez Puigdemont, Jordi |
dc.contributor.author | Calomarde Palomino, Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.date | 2012 |
dc.identifier.citation | Perez, J.; Calomarde, A.; Moll, F. Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture. A: Conference on Design of Circuits and Integrated Systems. "XXVIIth Conference on Design of Circuits and Integrated Systems". Avignon: 2012, p. 539-544. |
dc.identifier.citation | 978-2-9517461-1-4 |
dc.identifier.uri | http://hdl.handle.net/2117/17803 |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Enginyeria electrònica |
dc.subject | Rellotges |
dc.subject | Sistemes digitals i analògics |
dc.subject | Sistemes digitals |
dc.title | Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |