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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Aymerich Capdevila, Nivard |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.date | 2010 |
dc.identifier.citation | Aymerich, N.; Rubio, J. Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy. A: Conference on Design of Circuits and Integrated Systems. "Proceedings of the XXV Conference on Design of Circuits and Integrated Systems (DCIS 2010)". Lanzarote (Canaries): 2010, p. 228-233. |
dc.identifier.citation | 9788469373934 |
dc.identifier.uri | http://hdl.handle.net/2117/16005 |
dc.language.iso | eng |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència |
dc.subject | Fault-tolerant systems |
dc.subject | NAND multiplexing |
dc.subject | Nanotecnologia |
dc.title | Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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