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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Lira Rueda, Javier |
dc.contributor.author | Molina Clemente, Carlos |
dc.contributor.author | Brooks, David |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2010-08-27 |
dc.identifier.uri | http://hdl.handle.net/2117/13932 |
dc.language.iso | eng |
dc.relation | UPC-DAC-RR-ARCO-2010-3 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | SRAM chips |
dc.subject | NUCA cache |
dc.subject | eDRAM module |
dc.subject | SRAM chips |
dc.subject | DRAM chips |
dc.title | Implementing a hybrid SRAM / eDRAM NUCA architecture |
dc.type | info:eu-repo/semantics/draft |
dc.type | info:eu-repo/semantics/report |
dc.description.abstract |