vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells

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Title:	vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells
Author:	Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio
Other authors:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
Abstract:	In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorization
Subject(s):	-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -3T1D Cells -vPROBE
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Document type:	Article - Draft Report
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