Title:
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MFLUSH: handling long-latency loads in SMT on-chip multiprocessors
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Author:
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Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Nowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art high-performance processors like the IBM
POWER5 and POWER6 corroborate this CMP+SMT
trend. Within each SMT core any of the well-known SMT mechanisms may be applied to face SMT related challenges. Among them, probably the most important issue in an SMT execution pipeline concerns the In-struction Fetch (IFetch) Policy. The FLUSH IFetch
Policy represents a choice for throughput-oriented scenarios. It handles L2 cache misses in order to avoid hardware resource monopolization by any given execution Thread; involving an additional energy cost via instruction refetching. However, the new constraints imposed by the CMP+SMT scenario may a ect wellknown SMT mechanisms, like the FLUSH mechanism. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Computer storage devices -- Design and construction -Multiprocessors -- Design and construction -Cache memory -Memòria (informàtica) |
Rights:
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Document type:
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Article - Published version Conference Object |
Published by:
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IEEE Computer Society Publications
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