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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Cabarcas, Felipe |
dc.contributor.author | Rico Carro, Alejandro |
dc.contributor.author | Etsion, Yoav |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.date | 2010 |
dc.identifier.citation | Cabarcas, F. [et al.]. Interleaving granularity on high bandwidth memory architecture for CMPs. A: International Symposium on Systems, Architectures, Modeling, and Simulation. "SAMOS 2010 : International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS X)". Samos: IEEE Computer Society Publications, 2010, p. 250-257. |
dc.identifier.citation | 978-1-4244-7936-8 |
dc.identifier.citation | 10.1109/ICSAMOS.2010.5642060 |
dc.identifier.uri | http://hdl.handle.net/2117/11379 |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.relation | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5642060 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Computer storage devices -- Design and construction |
dc.subject | DRAM chips |
dc.subject | Interleaved storage |
dc.subject | Memory architecture |
dc.subject | Multiprocessing systems |
dc.subject | Memòria (informàtica) |
dc.title | Interleaving granularity on high bandwidth memory architecture for CMPs |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |