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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Gaydadjiev, Georgi |
dc.contributor.author | Isaza, Sebastian |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Cabarcas, Felipe |
dc.contributor.author | Juurlink, Ben |
dc.contributor.author | Álvarez Mesa, Mauricio |
dc.contributor.author | Sánchez Castaño, Friman |
dc.contributor.author | Azevedo, Arnaldo |
dc.contributor.author | Meenderinck, Cor |
dc.contributor.author | Ciobanu, Catalin |
dc.date | 2010-10 |
dc.identifier.citation | Ramirez, A. [et al.]. The SARC architecture. "IEEE micro", Octubre 2010, vol. 30, núm. 5, p. 16-29. |
dc.identifier.citation | 0272-1732 |
dc.identifier.uri | http://hdl.handle.net/2117/10688 |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Heterogeneous computing |
dc.subject | Multicore |
dc.subject | Heterogeneous architecture |
dc.subject | Accelerator |
dc.subject | Programming model |
dc.subject | Arquitectura d'ordinadors |
dc.title | The SARC architecture |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract |