To access the full text documents, please follow this link:

Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms
Sánchez Rivera, Giovanny; Madrenas Boadas, Jordi; Moreno Aróstegui, Juan Manuel
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades
The performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN algorithm mapping, the performance study demonstrates that the system can emulate up to 10,000 300-synapse neurons in real time at 64 MHz with conventional FPGAs. Important improvements can be achieved by using advanced technology and increased clock rate or by means of simple architecture modifications. The architecture is flexible enough to be efficiently applied to any SNN model in general.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Spiking neural networks
Hardware implementation
Xarxes neuronals (Informàtica) -- Tercera generació
Springer Verlag

Show full item record

Related documents

Other documents of the same author

Madrenas Boadas, Jordi; Fernández Martínez, Daniel; Cosp Vilella, Jordi; Moreno Aróstegui, Juan Manuel; Martínez Alvarado, Luis Arturo; Sánchez Rivera, Giovanny
Dorta Pérez, Silvestre Taho; Zapata Rodríguez, Mireya; Madrenas Boadas, Jordi; Sánchez Rivera, Giovanny
Sánchez Rivera, Giovanny; Koickal, Thomas Jacob; Sripad T A, Athul; Gouveia, Luiz Carlos; Hamilton, Alister; Madrenas Boadas, Jordi
Robert, M.; Volken, H.; Brousse, O.; Guillot, J.; Gil, T.; Grize, F.; Sassatelli, G.; Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Villa, A.