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Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms
Sánchez Rivera, Giovanny; Madrenas Boadas, Jordi; Moreno Aróstegui, Juan Manuel
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades
The performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN algorithm mapping, the performance study demonstrates that the system can emulate up to 10,000 300-synapse neurons in real time at 64 MHz with conventional FPGAs. Important improvements can be achieved by using advanced technology and increased clock rate or by means of simple architecture modifications. The architecture is flexible enough to be efficiently applied to any SNN model in general.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Spiking neural networks
Hardware implementation
SIMD
FPGA
SNNs
Xarxes neuronals (Informàtica) -- Tercera generació
info:eu-repo/semantics/publishedVersion
Article
Springer Verlag
         

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