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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Barajas Ojeda, Enrique |
dc.contributor.author | Mateo Peña, Diego |
dc.contributor.author | González Jiménez, José Luis |
dc.date | 2010 |
dc.identifier.citation | Barajas, E.; Mateo, D.; González, J. DLL's behavioral modeling for power consumption and jitter fast optimization. A: Conference on Design of Circuits and Integrated Systems. "XXV Conference on Design of Circuits and Integrated Systems". Lanzarote (Canaries): 2010, p. 408-413. |
dc.identifier.citation | 9788469373934 |
dc.identifier.uri | http://hdl.handle.net/2117/10525 |
dc.language.iso | eng |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal |
dc.subject | Delay lock loops |
dc.subject | Logic design |
dc.subject | Jitter |
dc.subject | DLL |
dc.title | DLL's behavioral modeling for power consumption and jitter fast optimization |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |