Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/13014
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Monchiero, Matteo |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2009 |
dc.identifier.citation | Monchiero, M.; Canal, R.; González, A. Using coherence information and decay techniques to optimize L2 cache leakage in CMPs. A: International Conference on Parallel Processing. "38th International Conference on Parallel Processing". Viena: IEEE Computer Society, 2009, p. 1-8. |
dc.identifier.citation | 978-0-7695-3802-0 |
dc.identifier.citation | 10.1109/ICPP.2009.28 |
dc.identifier.uri | http://hdl.handle.net/2117/13014 |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society |
dc.relation | http://portal.acm.org/citation.cfm?id=1679670 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Leakage |
dc.subject | Chip multiprocessor |
dc.subject | CMP |
dc.subject | Multicore |
dc.subject | Cache decay |
dc.subject | Coherence |
dc.subject | Multiprocessadors |
dc.title | Using coherence information and decay techniques to optimize L2 cache leakage in CMPs |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract |