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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Barajas Ojeda, Enrique |
dc.contributor.author | Mateo Peña, Diego |
dc.contributor.author | González Jiménez, José Luis |
dc.date | 2010 |
dc.identifier.citation | Barajas, E.; Mateo, D.; González, J. Behavioural modelling of DLLs for fast simulation and optimisation of jitter and power consumption. A: Euromicro Symposium on Digital Systems Design. "13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools". Llille: IEEE Computer Society Publications, 2010, p. 541-547. |
dc.identifier.citation | 978-0-7695-4171-6 |
dc.identifier.citation | 10.1109/DSD.2010.86 |
dc.identifier.uri | http://hdl.handle.net/2117/10678 |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal |
dc.subject | Logic design |
dc.subject | Delay lock loops |
dc.subject | DLL behavioural modelling |
dc.subject | Jitter optimisation |
dc.subject | Processament del senyal |
dc.title | Behavioural modelling of DLLs for fast simulation and optimisation of jitter and power consumption |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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