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Systematic design of two level pipelined systolic arrays with data contraflow
Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ICARUS - Sistemes Aviònics i de Comunicació Intel·ligents per Avions no Tripulats Fiables; Universitat Politècnica de Catalunya. CAP - Grup de Computació d´Altes Prestacions
Many systolic algorithms and related design methodologies have been recently proposed. Frecuently, in these systolic algorithms practical considerations are not taken into account. Equitatively distributed load between processing elements, pipelined functional units etc, are desirable features when implementing systolic algorithms.In this paper we present a design methodology in which these features are considered. As an example, the methodology is applied to obtain a problem-size-independent, two-level pipelined 1D systolic algorithm with data contraflow to efficiently solve triangular systems of equations.
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Pipelining (Electronics)
Processadors de matrius (arrays)
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
         

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