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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems |
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Valero García, Miguel |
dc.contributor.author | Navarro Guerrero, Juan José |
dc.contributor.author | Llaberia Griñó, José M. |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 1990 |
dc.identifier.citation | Valero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M. Implementation of systolic algorithms using pipelined functional units. A: International Conference on Application Specific Array Processors. "Proceedings of the International Conference on Application Specific Array Processors". Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 272-283. |
dc.identifier.citation | 10.1109/ASAP.1990.145464 |
dc.identifier.uri | http://hdl.handle.net/2117/8884 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/document/145464/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Pipelining (Electronics) |
dc.subject | Systolic array circuits |
dc.subject | Processadors de matrius (arrays) |
dc.subject | Algorismes |
dc.title | Implementation of systolic algorithms using pipelined functional units |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |