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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Valero, Alejandro |
dc.contributor.author | Sahuquillo, Julio |
dc.contributor.author | Petit, Salvador |
dc.contributor.author | Lorente, Vicente |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | López, Pedro |
dc.contributor.author | Duato, José |
dc.date | 2009 |
dc.identifier.citation | Valero, A. [et al.]. An hybrid eDRAM/SRAM macrocell to implement first-level data caches. A: IEEE/ACM International Symposium on Microarchitecture. "42nd Annual IEEE/ACM International Symposium on Microarchitecture". Nova York: Association for Computing Machinery (ACM), 2009, p. 213-221. |
dc.identifier.citation | 978-1-60558-798-1 |
dc.identifier.citation | 10.1145/1669112.1669140 |
dc.identifier.uri | http://hdl.handle.net/2117/10159 |
dc.language.iso | eng |
dc.publisher | Association for Computing Machinery (ACM) |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer storage devices |
dc.subject | Static and dynamic memory cells |
dc.subject | Retention time |
dc.subject | Leakage current |
dc.subject | Ordinadors -- Memòries |
dc.title | An hybrid eDRAM/SRAM macrocell to implement first-level data caches |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |