Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models

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Title:	Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models
Author:	Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Kotynia, L.
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades
Abstract:	In this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation of large-scale biologically inspired spiking neural networks models. By introducing specific commands in the AER protocol it is possible to distribute the AER bus among a large number of chips where the functionality of the spiking neurons is being emulated. A careful design of the AER encoder module using compact Content Addressable Memories (CAMs) allows for a feasible realization of large-scale models.
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica -Neural networks -Electrònica
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Document type:	Article - Published version Conference Object
Published by:	IEEE Computer Society Publications
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