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Translinear signal processing circuits in standard CMOS FPAA
Martínez Alvarado, Luis Arturo; Madrenas Boadas, Jordi; Fernández Martínez, Daniel
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades
In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 MHz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal
Electric circuits
Adaptive signal processing
Circuits
Senyal, Teoria del (Telecomunicació)
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
IEEE Press. Institute of Electrical and Electronics Engineers
         

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