To access the full text documents, please follow this link:

On-Chip memories, the OS perspective
Villavieja Prados, Carlos; Gelado Fernandez, Isaac; Ramírez Bellido, Alejandro; Navarro Mas, Nacho
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d´Altes Prestacions
This paper is a work in progress study of the operating system services required to manage on-chip memories. We are evaluating different CMP on-chip memories configurations. Chip-MultiProcessors (CMP) architectures integrating multiple computing and memory elements presents different problems (coherency, latency, ...) that must be solved. On-chip local memories are directly addressable and their latency is much shorter than off-chip main memories. Since memory latency is a key factor for application performance, we study how the OS can help.
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Memory management (Computer science)
On-chip memories
Memory architecture
Gestió de memòria (Informàtica)
Attribution-NonCommercial-NoDerivs 3.0 Spain

Show full item record

Related documents

Other documents of the same author

Rico Carro, Alejandro; Cabarcas, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
Tanasic, Ivan; Vilanova, Lluís; Jorda, Marc; Cabezas, Javier; Gelado Fernandez, Isaac; Navarro Mas, Nacho; Hwu, Wen-mei W.
Jimenez, Victor; Vilanova, Lluis; Gelado Fernandez, Isaac; Gil, Marisa; Fursin, Gregori; Navarro Mas, Nacho
Cabezas, Javier; Ayala Polo, Mauricio; Gelado Fernandez, Isaac; Morancho Llena, Enrique; Navarro Mas, Nacho; Cela Espín, José M.
Gelado Fernandez, Isaac; Cabezas, Javier; Navarro Mas, Nacho; Stone, John E.; Patel, Sanjay; Hwu, Wen-mei W.