This paper describes a design methodology for the basic current source cell circuit of high-speed high-accuracy current steering DIA conveners taking into account mismatching in all the transistors of the cell. Previous works consider arbitrary safety margins in the sizing process. The presented approach allows a more accurale selection of the optimal design point. The design methodology is illustrated for a particular design of a 0.35pm CMOS 12-bit 400 MHz current-steering segmented DIA converter.