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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | García Leyva, Lancelot |
dc.contributor.author | Andrade Miceli, Dennis Michael |
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Calomarde Palomino, Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.date | 2011-12 |
dc.identifier.citation | García, L. [et al.]. New redundant logic design concept for high noise and low voltage scenarios. "Microelectronics journal", Desembre 2011, vol. 42, núm. 12, p. 1359-1369. |
dc.identifier.citation | 0026-2692 |
dc.identifier.citation | 10.1016/j.mejo.2011.09.007 |
dc.identifier.uri | http://hdl.handle.net/2117/14228 |
dc.language.iso | eng |
dc.relation | http://www.sciencedirect.com/science/article/pii/S0026269211001960 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/120003/EU/MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems/MODERN |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject | Turtle Logic |
dc.subject | Microelectrònica -- Models matemàtics |
dc.title | New redundant logic design concept for high noise and low voltage scenarios |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract |