An environment for the automatic verification of digital circuits

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dc.contributor	Universitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics
dc.contributor	Cortadella, Jordi
dc.contributor	Carmona Vargas, Josep
dc.contributor.author	San Pedro Martín, Javier de
dc.date	2011-05-17
dc.identifier.citation	69348
dc.identifier.uri	http://hdl.handle.net/2099.1/12064
dc.language.iso	eng
dc.publisher	Universitat Politècnica de Catalunya
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject	Digital integrated circuits
dc.subject	Verilog
dc.subject	Verficació Automática
dc.subject	SMV
dc.subject	Automatic Verification
dc.subject	Circuits integrats digitals
dc.title	An environment for the automatic verification of digital circuits
dc.type	info:eu-repo/semantics/bachelorThesis
dc.description.abstract	Finalista del Premi Cercle Fiber al millor Projecte Final de Carrera (curs 2010-2011)
dc.description.abstract	English: The aim of this project is to implement a system for the automatic verification of digital circuits written in a high-level hardware description language (Verilog), to be potentially used to assist a electronic design automation course.