Título:
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Clock gate on abort: Towards energy-efficient hardware transactional memory
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Autor/a:
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Sanyal, Sutirtha; Roy, Sourav; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy when the speculation goes wrong and transaction aborts. For Transactional Memory this wastage will typically be quite high because programmer will often mark a large portion of the code to be executed transactionally. We are proposing to turn-off a processor dynamically by gating all its clocks, whenever any transaction running in it is aborted. We have described a novel protocol which can be used in the Scalable-TCC like Hardware Transactional Memory systems. Also in the protocol we are proposing a gating-aware contention management policy to set the duration of the clock gating period precisely so that both performance and energy can be improved. With our proposal we got an average 19% savings in the total consumed energy and even an average speed-up of 4%. |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Multiprocessors -- Programming -Parallel programming (Computer science) -Hardware transactional memory -Clock gating -Distributed shared memory architecture -Transaction abort -Low-power architecture -Multiprocessadors -- Programació -Programació en paral·lel (Informàtica) |
Derechos:
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Tipo de documento:
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Artículo - Versión publicada Objeto de conferencia |
Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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