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Título:
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Multithreaded vector architectures
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Autor/a:
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Espasa Sans, Roger; Valero Cortés, Mateo
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
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Abstract:
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The purpose of this paper is to show that multi-threading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate a selection of the Perfect Club and Specfp92 programs and compare their execution time on a conventional vector architecture with a single memory port and on a multithreaded vector architecture. We devote an important part of this paper to study the interaction between multi-threading and main memory latency. This paper focuses on maximizing the usage of the memory port, the most expensive resource is typical vector computers. A study of the cost associated with the duplication of the vector register file is also carried out. Overall, multithreading provides for this architecture a performance advantage of more than a factor of 1.4 for realistic memory latencies, and can drive the utilization of the single memory port as high as 95%. |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
-Parallel processing (Electronic computers)
-Performance evaluation
-Vector processor systems
-Parallel architectures
-Discrete event simulation
-Processament en paral·lel (Ordinadors) |
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Derechos:
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Tipo de documento:
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Artículo - Versión publicada
Objeto de conferencia |
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Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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