Title:
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The design and performance of a conflict-avoiding cache
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Author:
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Topham, Nigel; González Colás, Antonio María; González González, José
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
Abstract:
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High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Cache memory -Parallel processing (Electronic computers) -Cache storage -Memory architecture -Performance evaluation -Parallel machines -Parallel architectures -Performance evaluation -Instruction sets -Memòria ràpida de treball (Informàtica) -Processament en paral·lel (Ordinadors) |
Rights:
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Document type:
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Article - Published version Conference Object |
Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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