Reducing branch delay to zero in pipelined processors

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Title:	Reducing branch delay to zero in pipelined processors
Author:	González Colás, Antonio María; Llaberia Griñó, José M.
Other authors:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Abstract:	A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Cache memory -Computer architecture -Pipeline processing -Buffer storage -Performance evaluation -Memòria ràpida de treball (Informàtica) -Arquitectura d'ordinadors
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Document type:	Article - Published version Article
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