In this Master Thesis the verification procedure of the top-down design process was implemented for the receiver sub-system of an IEEE 802.15.4 transceiver. The implemented flexible verification setup in Cadence enables continuous functionality checks of design changes of the receiver with the aid of behavioural models. The behavioural models for the receiver and for the RF and BB sub-circuit were created with the harware description language Verlog-AMS for analog/mixed-signal behaviour. The performance of functional verification test which were derived from the verification plan and were also developed with Verilog AMS, enabled accelerated simulation for interconnectivity and interoperability checks. Additionaly, the automation of the functional verification test was explored and a way was shown how this could be realised