This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process.

Peer Reviewed