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Título:
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Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
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Autor/a:
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Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Mauricio Ferré, Juan
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
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Abstract:
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A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE) |
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Abstract:
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Peer Reviewed |
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Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Nanoelectronics
-Lithography
-Design for manufacturability
-Lithography hotspots
-Yield estimation
-Layout design
-Nanoelectrònica
-Litografia |
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Derechos:
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Tipo de documento:
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Artículo - Versión presentada
Artículo |
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