Analysis and modelling of parasitic substrate coupling in CMOS circuits

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Title:	Analysis and modelling of parasitic substrate coupling in CMOS circuits
Author:	Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Roca Adrover, Miquel; Rubio Sola, Jose Antonio
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
Abstract:	Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Integrated circuits -CMOS integrated circuits -Capacitance -Integrated circuit modelling -Integrated circuit noise -Substrates -Circuits integrats
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Article
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