The evolution of CMOS technology has allowed the integration of communication systems on a single chip. A Low-Noise Amplifier (LNA) is the first block in an integrated receiver and its design is critical for the system performance. On-chip spiral inductors are key components in LNA’s running at GHz frequency range. They are the performance limiting components of LNA’s, and have the added problems of rigidity and also do not scale well with CMOS (i.e. consume a large amount of area, which increases the chip cost). Their quality factor (Q) is limited by the resistive losses in the spiral coil and by substrate losses. This project deals with replacing the areaconsuming, lossy spiral inductors by gyrator-based CMOS active inductors. The project starts with the simulation of some reference spiral inductors to find their main characteristics (inductance value, quality factor at different frequencies and selfresonant frequency). Next, several CMOS active inductors are designed with the target to achieve similar or improved performance compared to the reference ones. Several topologies are tested, and the designed is optimized after predictions of simple models. Finally, both active and passive inductors are then used in two test amplifiers: a tuned narrowband amplifiers and a wideband – extension amplifier. Their performance is compared in terms of input and output matching, gain, isolation, noise figure and linearity. Frequency tuning capability is tested in the active inductors, which would provide an interesting flexibility in future communication receivers.

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