Título:
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Impact of gate tunnelling leakage on CMOS circuits with full open defects
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Autor/a:
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Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Eichenberger, S.; Hora, Camelia; Kruseman, B.
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
Abstract:
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Electronics Letter of the Month |
Abstract:
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Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered
electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented. |
Abstract:
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Peer Reviewed |
Abstract:
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Award-winning |
Materia(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Metal oxide semiconductors, Complementary -CMOS integrated circuits -Circuits integrats -- CMOS -- Disseny i construcció |
Derechos:
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Tipo de documento:
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Artículo - Versión publicada Artículo |
Editor:
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Institution of Electrical Engineers
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Compartir:
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