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Title:
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A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
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Author:
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Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
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Abstract:
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In view of device scaling issues, embedded DRAM (eDRAM)
technology is being considered as a strong alternative to conventional
SRAM for use in on-chip memories. Memory cells designed using eDRAM
technology in addition to being logic-compatible, are variation tolerant
and immune to noise present at low supply voltages. However, two major
causes of concern are the data retention capability which is worsened by
parameter variations leading to frequent data refreshes (resulting in large
dynamic power overhead) and the transient reduction of stored charge
increasing soft-error (SE) susceptibility. In this paper, we present a novel
variation-tolerant 4T-DRAM cell whose power consumption is 20.4%
lower when compared to a similar sized eDRAM cell. The retention time
on-average is improved by 2.04X while incurring a delay overhead of
3% on the read-access time. Most importantly, using a soft-error (SE)
rate analysis tool, we have confirmed that the cell sensitivity to SEs is
reduced by 56% on-average in a natural working environment |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics
-Electronic circuits
-Circuits electrònics |
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Rights:
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Document type:
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Article - Published version
Conference Object |
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Published by:
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IEEE Computer Society Publications
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