Title:
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Systematic design of two level pipelined systolic arrays with data contraflow
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Author:
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Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Facultat d'Informàtica de Barcelona; Universitat Politècnica de Catalunya. ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract:
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Many systolic algorithms and related design methodologies
have been recently proposed. Frecuently, in these systolic
algorithms practical considerations are not taken into account.
Equitatively distributed load between processing elements,
pipelined functional units etc, are desirable features when
implementing systolic algorithms.In this paper we present a
design methodology in which these features are considered. As
an example, the methodology is applied to obtain a
problem-size-independent, two-level pipelined 1D systolic
algorithm with data contraflow to efficiently solve triangular
systems of equations. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Pipelining (Electronics) -Processadors de matrius (arrays) |
Rights:
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Document type:
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Article - Published version Conference Object |
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