Abstract:
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Testing of signal integrity (SI) in current high-speed
ICs, requires automatic test equipment test resources at the multigigahertz
range, normally not available. Furthermore, for most internal
nets of state-of-the-art ICs, external speed testing is not possible
for the newest technologies. In this paper, on-chip testing for
SI faults in digital interconnect signals, using built-in high speed
monitors, is proposed. A coherent sampling scheme is used to capture
the signal information. Two monitors to test SI violations are
proposed: one for undershoots at the high logic level and the other
for overshoots at the low logic level. The monitors are capable of
detecting small noise pulses and have been extended to test sequentially
more than one signal. The cost of the proposed strategy is
analyzed in terms of area, delay penalization, and test time. The
effects of clock jitter and process variations are analyzed. Experimental
results obtained in designed and fabricated circuits show
the feasibility of the proposed testing strategy. A good agreement
appears between the theoretical analysis, simulation results, and
the experimental measurements. |