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Title:	Verifying analog circuits based on a digital signature
Author:	Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan
Other authors:	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. Departament de Disseny i Programació de Sistemes Electrònics; Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
Abstract:	Verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter verification based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t); y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x; y) location. A metric to be used to discriminate the golden and defective signatures is also proposed. The metric is based on the definition of a discrepancy factor performing circuit parameter identification via statistical and pre-training procedures. The proposed method is applied to verify possible deviations on the natural frequency of a Biquad filter. Simulation results show the possibilities of the proposal.
Subject(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics -Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica::Criptografia -Monitoring -Digital signatures -Mixed signal circuits -- Testing -Monitoratge -Signatures electròniques -Circuits integrats mixtes
Rights:	Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es/
Document type:	Article - Published version Conference Object
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