Prjecte final de carrera realitzat en col.laboració amb Institute of the Industrial Information Technology

The aim of this project is to create a Polling-based MAC Layer Protocol for PLC. The first step is to look up some information about how the protocol is and then create the best design. This protocol is inside the Datalink layer, which function is to control the flow of frames inside the network and to make it as efficient as possible. A master/slave typology is used. There is a device (master) that indicates when a slave can transmit a frame. The main advantage of this typology is the low collision risk. The second step is the VHDL implementation which is made in Modelsim. This program is a simulator too, so the functional correctness of the design can be checked with it. Inside this step, there are two stages: firstly the ARQ scheme is made and when it works, the rest of the design is implemented. It is important to simulate the code because all the process, until the result is reached, can be studied, but it does not mean it works in a real device. An Altera kit with a Cyclon III FPGA is used to make the finals tests.